Design VerificationEngineering Tomorrow, Today: ASIC & FPGA Design

At Eximietas we have experience in building large maintainable verification environments in both SystemC and SystemVerilog. We have significant experience in Building test environments for
  • IP blocks
  • Subsystem level environments and
  • SoC level environments.
Most recently, we are able to use AI/ML to automate:
Test Environment building
Test Creation
Coverage analysis and improvement

We have significant experience and Expertise in:

  • IP and SoC Level Verification (N/W Processors, CPU, GPU, Sensors etc)
  • CPU: x86, ARM, RISC V, Tensilica, ARC, MIPS
  • Methodologies: SV-UVM, OVM, C/C++
  • Functional, Formal, Static and Power-Aware verification
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