VLSI / 4+ Years

Physical Design Engineer

Bengaluru / Ahmedabad / Chennai

Job Description

We are seeking an exceptional Senior Physical Design Engineer to take a key role in our semiconductor design team. As a Senior Physical Design Engineer, you will lead the development and implementation of cutting-edge physical design methodologies and flows for complex ASIC designs. You will collaborate closely with cross-functional teams to ensure the successful delivery of high-quality designs

Key Responsibilities

  • Perform Synthesis, floor planning, placement, Clock, routing, and PPA optimization for High Speed Advance ASICs.
  • Define and drive physical design strategies to meet aggressive performance, power, and area targets.
  • Conduct detailed analysis of timing, power, and area, and drive design optimizations to improve QoR.
  • Block/Partition signoff closure for STA, PV, LEC, IR/EM, CLP very efficiently.
  • Provide technical leadership and guidance to the physical design team, mentoring junior engineers and fostering a culture of excellence.
  • Work closely with RTL design and DFT teams to understand design requirements and constraints, and drive successful tapout of designs.
  • Support and Development of advanced physical design methodologies and flows for complex semiconductor designs.


  • Bachelor’s or Master’s degree in Electrical Engineering or Electronics & Communications.
  • 4+ years of experience in physical design of ASICs
  • Proficiency in industry-standard EDA tools from Cadence, Synopsys and Mentor Graphics for Synthesis, PnR, Signoff Closure.
  • Extensive experience with timing closure techniques, power optimization.
  • Strong scripting skills using TCL, Python, or Perl for design automation and tool customization.
  • Excellent problem-solving and analytical skills, with a track record of delivering high-quality designs on schedule.
  • Outstanding communication and interpersonal skills, with the ability to collaborate effectively in a team environment.
  • Proven ability to lead and mentor junior engineers, fostering their professional growth and development.
  • Experience with advanced process nodes 3nm, 5nm, 7nm, 10nm including knowledge of FinFET technology.
  • Expertise in Synthesis that includes details understanding of RTL, Early PnR timing issues, Constraint issue, design issues.
  • Experience in handling Partitions and blocks for size estimation, pin assignment, CTS.
  • Knowledge on Handling various custom IP such as PLL, Divider, Serdes, ADC, DAC, GPIO, HSIO for PD integration.
  • Detailed Knowledge on Clocking methodology and various techniques to improve skew, latency, timing, power.
  • Familiarity with low-power design techniques and methodologies, such as multi-voltage domains and power gating using UPF.
  • Expertise in physical verification, including DRC, Antenna, LVS, PERC, and ERC checks.
  • Expertise in Timing Closure including setup, hold, DRV, SI, Interface issues.
  • Experience with formal verification for RTL to Netlist and Netlist to Netlist.
  • Knowledge of emerging technologies such as machine learning and AI for design automation and optimization.